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d a t a sh eet preliminary speci?cation supersedes data of 2003 aug 06 2003 oct 13 integrated circuits TEA1211hn high efficiency auto-up/down dc/dc converter
2003 oct 13 2 philips semiconductors preliminary speci?cation high ef?ciency auto-up/down dc/dc converter TEA1211hn contents 1 features 2 applications 3 general description 4 ordering information 5 block diagram 6 pinning 7 functional description 7.1 introduction 7.2 control mechanism 7.2.1 pwm 7.2.2 pfm 7.2.3 switching sequence 7.3 adjustable output voltage 7.4 start-up 7.5 under voltage lockout 7.6 shut-down 7.7 power switches 7.8 synchronous rectification 7.9 pwm-only mode 7.10 external synchronisation 7.11 current limiter 7.12 i 2 c-bus serial interface 7.12.1 characteristics of the i 2 c-bus 7.12.2 start and stop conditions 7.12.3 bit transfer 7.12.4 acknowledge 7.13 i 2 c-bus protocol 7.13.1 addressing 7.13.2 data 7.13.3 write cycle 8 limiting values 9 thermal characteristics 10 characteristics 11 application information 11.1 typical li-ion, 2- or 3-cell application with i 2 c-bus programming 11.2 component selection 11.2.1 inductor 11.2.2 capacitors 11.2.3 schottky diodes 11.2.4 feedback resistors 11.2.5 current limiter 12 package outline 13 soldering 13.1 introduction to soldering surface mount packages 13.2 reflow soldering 13.3 wave soldering 13.4 manual soldering 13.5 suitability of surface mount ic packages for wave and reflow soldering methods 14 data sheet status 15 definitions 16 disclaimers 17 purchase of philips i 2 c components
2003 oct 13 3 philips semiconductors preliminary speci?cation high ef?ciency auto-up/down dc/dc converter TEA1211hn 1 features i 2 c-bus programmable output voltage range of 1.5 v to 5.5 v single inductor topology high efficiency up to 94 % over wide load range wide input range; functional from 2.55 v up to 5.5 v 1.7 a maximum input and output current low quiescent power consumption 600 khz switching frequency four integrated very low r ds(on) power mosfets synchronizable to external clock externally adjustable current limit for protection and efficient battery use in case of dynamic loads under voltage lockout pwm-only option shut-down current less than 1 m a 32-pin small body hvqfn package. 2 applications stable output voltage from lithium-ion batteries variable voltage source for pas (power amplifiers) in cellular phones wireless handsets hand-held instruments portable computers. 3 general description the TEA1211hn is a fully integrated auto-up/down dc/dc converter circuit with i 2 c-bus interface. efficient, compact and dynamic power conversion is achieved using a digitally controlled pulse width and frequency modulation like control concept, four integrated low r ds(on) power switches with low parasitic capacitances and fully synchronous rectification. the combination of auto-up/down dc/dc conversion, high efficiency and low switching noise makes the TEA1211hn well suited to supply a power amplifier in a cellular phone. the output voltage can be i 2 c-bus programmed to the exact voltage needed to achieve a certain output power level with optimal system efficiency, thus enlarging battery lifetime. the TEA1211hn operates at 600 khz switching frequency which enables the use of small size external components. the switching frequency can be locked to an external high frequency clock. deadlock is prevented by an on-chip under voltage lockout circuit. an adjustable current limit enables efficient battery use even at high dynamic loads. optionally, the device can be kept in pulse width modulation mode regardless of the load applied. 4 ordering information type number package name description version TEA1211hn hvqfn32 plastic thermal enhanced very thin quad ?at package; no leads; 32 terminals; body 5 5 0.85 mm sot617-3
2003 oct 13 4 philips semiconductors preliminary speci?cation high ef?ciency auto-up/down dc/dc converter TEA1211hn 5 block diagram handbook, full pagewidth mdb001 i 2 c-bus interface temperature protection internal supply bandgap reference 13 mhz oscillator clock selector digital controller n-type power fets n-down TEA1211hn lxb lxa n.c. in 2, 31, 32 29 6, 8, 17, 19 28 12 13 30 27 23, 25, 26 14, 15, 21, 22, 24 1, 3, 4, 10, 11 5, 7, 9, 16, 18, 20 sync/pwm shdwn scl sda ilim gnd fb out current limit comparator window comparator p-type power fet p-down sense fet p-type power fet p-up n-up fig.1 block diagram. 6 pinning symbol pin description lxa 1 inductor connection 1 in 2 input voltage lxa 3 inductor connection 1 lxa 4 inductor connection 1 gnd 5 ground n.c. 6 not connected gnd 7 ground n.c. 8 not connected gnd 9 ground lxa 10 inductor connection 1 lxa 11 inductor connection 1 scl 12 serial clock input line i 2 c-bus sda 13 serial data input/output line i 2 c-bus lxb 14 inductor connection 2 lxb 15 inductor connection 2 gnd 16 ground n.c. 17 not connected gnd 18 ground n.c. 19 not connected gnd 20 ground lxb 21 inductor connection 2 lxb 22 inductor connection 2 out 23 output voltage lxb 24 inductor connection 2 out 25 output voltage out 26 output voltage fb 27 feedback input shdwn 28 shut-down input sync/pwm 29 synchronization clock input, pwm-only input ilim 30 current limit resistor connection in 31 input voltage in 32 input voltage symbol pin description
2003 oct 13 5 philips semiconductors preliminary speci?cation high ef?ciency auto-up/down dc/dc converter TEA1211hn handbook, halfpage gnd sda lxa scl lxa lxb gnd lxb in shdwn ilim sync/pwm in fb out out n.c. n.c. gnd gnd lxa lxa in lxa mdb002 gnd n.c. gnd n.c. lxb lxb out lxb 2 1 3 4 5 6 7 16 14 12 15 13 11 10 9 25 28 26 27 29 30 31 32 8 24 23 21 22 20 19 18 17 TEA1211hn fig.2 pin configuration. this diagram is a bottom side view. pin 1 is indicated with a dot on the top side of the package. for mechanical details of hvqfn32 package, see chapter 12. 7 functional description 7.1 introduction the TEA1211hn is able to operate in pulse frequency modulation (pfm) or discontinuous conduction mode as well as in pulse width modulation (pwm) or continuous conduction mode. all switching actions are completely determined by a digital control circuit which uses the output voltage level as control input. this digital approach enables the use of a new pulse width and frequency modulation scheme, which ensures optimum power efficiency over the complete range of operation of the converter. 7.2 control mechanism depending on load current i load and v in to v out ratio, the controller chooses a mode of operation. when high output power is requested, the device will operate in pwm (continuous conduction) mode, which is a 2-phase cycle in up- as well as in down mode. for small load currents the controller will switch over to pfm (discontinuous mode), which is either a 3- or 4-phase cycle depending on the input to output ratio, see fig.3. handbook, halfpage mdb003 0 pwm i coil pfm v in > v out down mode v in = v out stationary mode v in < v out up mode fig.3 waveform of coil current as function of i load and v in to v out ratio.
2003 oct 13 6 philips semiconductors preliminary speci?cation high ef?ciency auto-up/down dc/dc converter TEA1211hn 7.2.1 pwm pwm results in minimum ac currents in the circuit components and hence optimum efficiency, cost and emc. in this mode the output voltage is allowed to vary between two predefined voltage levels. when the output voltage stays within this so called window, switching continues in a fixed pattern. when the output voltage reaches one of the window borders, the digital controller immediately reacts by adjusting the duty cycle and inserting a current step in such a way that the output voltage stays within the window with higher or lower current capability. this approach enables very fast reaction to load variations. figure 4 shows the TEA1211hns response to a sudden load increase in case of up conversion. the upper trace shows the output voltage. the ripple on top of the dc level is a result of the current in the output capacitor, which changes in sign twice per cycle, multiplied by the capacitors internal equivalent series resistance (esr). after each ramp-down of the inductor current, or when the esr effect increases the output voltage, the TEA1211hn determines what to do in the next cycle. as soon as more load current is taken from the output the output voltage starts to decay. when the output voltage becomes lower than the low limit of the window, corrective action is taken by a ramp-up of the inductor current during a much longer time. as a result, the dc current level is increased and normal pwm control can continue. the output voltage (including esr effect) is again within the predefined window. figure 5 depicts the spread of the output voltage window. the absolute value is most dependent on spread, while the actual window size is not affected. for one specific device, the output voltage will not vary more than 2 % typically. 7.2.2 pfm in low output power situations, TEA1211hn will switch over to pfm mode operation in case pwm-only mode is not activated. in this mode charge is transferred from battery to output in single pulses with a wait phase in between. regulation information from earlier pwm mode operation is used. this results in optimum inductor peak current levels in pfm mode, which are slightly larger than the inductor ripple current in pwm mode. as a result, the transition between pfm and pwm mode is optimal under all circumstances. in pfm mode, the TEA1211hn regulates the output voltage to the limits shown in fig.5. depending on the v in to v out ratio the TEA1211hn decides for a 3- or 4-phase cycle, where the last phase is the wait phase. when the input voltage almost equals the output voltage, one of the slopes of a 3-phase cycle becomes weak. then the charge, or the integral of its pulse, is near to zero and no charge is transferred. in this region the 4-phase cycle is used, (see fig.3). handbook, full pagewidth mdb004 start corrective action load increase high window limit low window limit v out i load time time fig.4 response to load increase in up-mode.
2003 oct 13 7 philips semiconductors preliminary speci?cation high ef?ciency auto-up/down dc/dc converter TEA1211hn handbook, full pagewidth mdb005 maximum positive spread of v fb maximum negative spread of v fb typical situation lower specification limit upper specification limit + 4% - 4% 2% v out (typ.) v h v l 2% v h v l v h v l 2% fig.5 spread of location of output voltage window. v h = high window limit v l = low window limit 7.2.3 s witching sequence refer to figures 1 and 3. in up-mode the cycle starts by making p-down and n-up conducting in the first phase. the second phase n-up opens and p-up starts conducting. in down-mode the cycle starts with in the first phase p-up and p-down conducting. the second phase p-down opens and n-down starts conducting. in pfm these two phases are followed by a third or wait phase that opens all switches except for n-down, which is closed to prevent the coil from floating. the stationary mode or 4-phase cycle, which only occurs in pfm, starts with in the first phase p-down and n-up conducting. in the second phase p-down and p-up conduct forming a short-cut from battery to output capacitor. in the third phase p-up and n-down conduct. the fourth or wait-phase again opens all switches except for n-down which is closed to prevent the coil from floating. 7.3 adjustable output voltage the output voltage of the TEA1211hn can be set to a fixed value by means of an external resistive divider. after start-up through this divider, dynamic control of the output voltage is made possible by use of an i 2 c-bus. the output voltage can be programmed from 1.5 v to 5.5 v in 40 steps of 0.1 v each. in case of power amplifiers (pas) for example the output voltage of the TEA1211hn can be adjusted to the output power to be transmitted by the pa, in order to obtain maximum system efficiency. 7.4 start-up if the input voltage exceeds the start voltage, the TEA1211hn starts ramping up the voltage at the output capacitor. ramping stops when the target level, set by the external resistors, is reached. 7.5 under voltage lockout as a result of too high load or disconnection of the input power source, the input voltage can drop too low to guarantee normal regulation. in that case, the device switches to a shut-down mode stopping the switching completely. start-up is possible by crossing the start-up level again. 7.6 shut-down when pin shdwn is made high, the converter disables all switches except for n-down (see fig.1) and power consumption is reduced to a few m a. n-down is kept conducting to prevent the coil from floating. 7.7 power switches the power switches in the ic are two n-type and two p-type mosfets, having a typical pin-to-pin resistance of 85 m w . the maximum continuous input/output current in the switches is 1.7 a at 70 c ambient temperature.
2003 oct 13 8 philips semiconductors preliminary speci?cation high ef?ciency auto-up/down dc/dc converter TEA1211hn 7.8 synchronous recti?cation for optimal efficiency over the whole load range, synchronous rectifiers inside the TEA1211hn ensure that in pfm mode during the phase where the coil current is decreasing, all inductor current will flow through the low ohmic power mosfets. special circuitry is included which detects that the inductor current reaches zero. following this detection, the digital controller switches off the power mosfet and proceeds regulation. negative currents are thus prevented. 7.9 pwm-only mode when pin sync/pwm is high, the TEA1211hn will use pwm regulation independent of the load applied. as a result, the switching frequency does not vary over the whole load range. 7.10 external synchronisation if a high frequency clock is applied to pin sync/pwm, the switching frequency in pwm mode will be exactly that frequency divided by 22. pfm mode is not possible if an external clock is applied. the quiescent current of the device increases when an external clock is applied. in case no external synchronisation is necessary and the pwm-only option is not used, pin sync/pwm must be connected to ground. 7.11 current limiter if the peak input current of the TEA1211hn exceeds its limit in pwm mode, current ramping is stopped immediately, and the next switching phase is entered. the current limitation protects the ic against overload conditions, inductor saturation, etc. the current limit level is user defined by the external resistor which must be connected between pin ilim and pin gnd. 7.12 i 2 c-bus serial interface the serial interface of the TEA1211hn is the i 2 c-bus. a detailed description of the i 2 c-bus specification, including applications, is given in the brochure: the i 2 c-bus and how to use it , order no. 9398 393 40011. 7.12.1 c haracteristics of the i 2 c- bus the i 2 c-bus is for bidirectional, two-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor (for best efficiency it is advised to use the input voltage of the convertor). data transfer may be initiated only when the bus is not busy. in bus configurations with ics on different supply voltages, the pull-up resistors shall be connected to the highest supply voltage. the i 2 c-bus supports incremental addressing. this enables the system controller to read or write multiple registers in only one i 2 c-bus action. the TEA1211hn supports the i 2 c-bus up to 400 kbit/s. the i 2 c-bus system configuration is shown in fig.6. a device generating a message is a transmitter, a device receiving a message is a receiver. the device that controls the message is the master and the devices which are controlled by the master are the slaves. the TEA1211hn is a slave only device. handbook, full pagewidth mdb006 master transmitter / receiver slave receiver slave transmitter / receiver master transmitter master transmitter / receiver sda scl fig.6 i 2 c-bus system configuration.
2003 oct 13 9 philips semiconductors preliminary speci?cation high ef?ciency auto-up/down dc/dc converter TEA1211hn 7.12.2 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line, while the clock is high is defined as the start condition (s). a low-to-high transition of the data line while the clock is high is defined as the stop condition (p) (see fig.7). 7.12.3 b it transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see fig.8). 7.12.4 a cknowledge the number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlimited. each byte of eight bits is followed by an acknowledge bit. the acknowledge bit is a high level signal put on the bus by the transmitter during which time the receiver generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter (see fig.9). the device that acknowledges must pull down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse (set-up and hold times must be considered). a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event the transmitter must leave the data line high to enable the master to generate a stop condition. handbook, full pagewidth sda scl p stop condition sda scl s start condition mdb007 fig.7 start and stop conditions on the i 2 c-bus. handbook, full pagewidth mdb008 data line stable; data valid change of data allowed sda scl fig.8 bit transfer on the i 2 c-bus.
2003 oct 13 10 philips semiconductors preliminary speci?cation high ef?ciency auto-up/down dc/dc converter TEA1211hn handbook, full pagewidth mdb009 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by slave transmitter data output by slave receiver scl from master transmitter fig.9 acknowledge on the i 2 c-bus. 7.12.5 i 2 c- bus protocol 7.12.5.1 addressing before any data is transmitted on the i 2 c-bus, the device which should respond is addressed first. the addressing is always carried out with the first byte transmitted after the start procedure. the (slave) address of the TEA1211hn is 0001 0000 (10h). the subaddress (or word address) is 0000 0000 (00h). the TEA1211hn acts as a slave receiver only. therefore the clock signal scl is only an input signal. the data signal sda is a bidirectional line, enabling the TEA1211hn to send an acknowledge. 7.12.5.2 data the data consists of one byte, addressing the 40 voltage steps as explained in tables 1 and 2. table 1 data byte table 2 translation data byte to voltage level subaddress bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 2 bit 0 00h 0 0 cvlvl5 cvlvl4 cvlvl3 cvlvl2 cvlvl1 cvlvl0 subaddress name size (bit) step number min. (v) step (v) max. (v) min. max. 00h cvlvl 6 0 40 1.5 0.1 5.5
2003 oct 13 11 philips semiconductors preliminary speci?cation high ef?ciency auto-up/down dc/dc converter TEA1211hn 7.12.5.3 write cycle the i 2 c-bus configuration for the different TEA1211hn write cycles is shown in fig.10. the word address is an eight bit value that defines which register is to be accessed next. handbook, full pagewidth acknowledgement from slave r/w auto increment memory word address mdb010 acknowledgement from slave acknowledgement from slave n bytes s a slave address a a data p 0 word address fig.10 master transmits to slave receiver (write mode). s = start condition. p = stop condition. 8 limiting values notes 1. human body model: equivalent to discharging a 100 pf capacitor via a 1.5 k w resistor. 2. machine model: equivalent to discharging a 200 pf capacitor via a 0.75 m h series inductor. 9 thermal characteristics symbol parameter conditions min. max. unit v n voltage on any pin with respect to gnd shut-down mode - 0.5 +6.0 v operational mode - 0.5 +5.5 v p tot total internal power dissipation - 1000 mw t j junction temperature - 40 +150 c t amb ambient temperature - 40 +85 c t stg storage temperature - 40 +125 c v esd electrostatic discharge voltage pins lxa note 1 - 800 v note 2 - 200 v all other pins jedec class ii; note 1 - 2000 v jedec class ii; note 2 - 200 v symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient mounted on dedicated pcb in free air 35 k/w
2003 oct 13 12 philips semiconductors preliminary speci?cation high ef?ciency auto-up/down dc/dc converter TEA1211hn 10 characteristics t amb = - 40 to +85 c; all voltages with respect to ground; positive currents ?ow into the ic; unless otherwise speci?ed. notes 1. current limit level is defined by the external r lim resistor, see chapter 11. 2. measured at t amb =25 c. 3. to avoid additional supply current, it is advised to use high levels not lower than v in - 0.5 v. symbol parameter conditions min. typ. max. unit voltage levels v out output voltage 1.50 - 5.50 v v in(start) start voltage v out = 3.5 v; i load < 100 ma 2.45 2.55 2.65 v v in input voltage v in(start) - 5.50 v v in(uvlo) under voltage lockout level - v in(start) - 0.15 - v v fb feedback voltage level 1.20 1.25 1.30 v v out(wdw) output voltage window as percentage of v out pwm mode 1.5 2.0 3.0 % current levels i q quiescent current no load - 100 -m a i shdwn current in shut-down mode - <1 2 m a d i lim current limit deviation i lim = 1 a; note 1 - 30 - +30 % i max maximum continuous input/output current t amb <70 c -- 1.7 a power mosfets; note 2 r ds(on)(n) pin-to-pin resistance nfets v in = 3.5 v - 65 85 m w r ds(on)(p) pin-to-pin resistance pfets v in = 3.5 v - 65 85 m w r ds(on)(p-up) pin-to-pin resistance p-up fet between pins lxb and out v out = 1.5 v - 100 135 m w timing f sw switching frequency pwm mode 450 600 750 khz f sync synchronization input frequency 4.5 13 20 mhz digital levels: pins sync/pwm, shdwn, scl and sda v il low-level input voltage 0 - 0.4 v v ih high-level input voltage note 3 0.6 v in - v in + 0.3 v temperature t amb ambient temperature - 40 +25 +85 c t max internal cut-off temperature 120 135 150 c
2003 oct 13 13 philips semiconductors preliminary speci?cation high ef?ciency auto-up/down dc/dc converter TEA1211hn 11 application information 11.1 typical li-ion, 2- or 3-cell application with i 2 c-bus programming handbook, full pagewidth mdb011 TEA1211hn 1 2 3 4 10 11 14 15 21 22 24 12 13 29 28 30 5 7 9 16 18 20 31 32 26 25 23 27 r lim 1 k w r2 75 k w c out 100 m f c in 100 m f battery v in = 2.55 to 5.5 v r1 120 k w scl sda shdwn sync/ pwm ilim lxa lxb gnd fb out in v out = 3.3 v d1 d2 l1 10 m h fig.11 the TEA1211hn in a typical auto-up/down converter application. the combination of the feedback resistors r1 and r2 in parallel should be approximately 50 k w . d1 and d2 are schottky diodes the battery can be a one cell li-ion, two cell alkaline or three cell nicd/nimh/alkaline. if the i 2 c-bus interface is used for programming the output voltage, the scl and sda lines must be connected to a positive supply via pull-up resistors (see section 7.12.1). if the i 2 c-bus interface is not used, connect pins scl and sda to ground. note the v ih -level (see chapter 10). pins should never be left open-circuit. no external clock is applied.
2003 oct 13 14 philips semiconductors preliminary speci?cation high ef?ciency auto-up/down dc/dc converter TEA1211hn handbook, full pagewidth 0 100 20 40 60 80 mdb013 1 10 100 1000 i load (ma) h ( % ) (4) (5) (1) (2) (3) fig.12 efficiency as a function of load current. v out = 3.3 v. l1=10 m h, tdk slf7032 series. (1) v in = 2.7 v. (2) v in = 3.3 v. (3) v in = 3.6 v. (4) v in = 4.2 v (5) v in = 4.5 v.
2003 oct 13 15 philips semiconductors preliminary speci?cation high ef?ciency auto-up/down dc/dc converter TEA1211hn handbook, full pagewidth 100 0 2.50 3.00 3.50 4.00 4.50 v in (v) 20 40 60 80 mdb012 h ( % ) (5) (4) (1) (2) (3) fig.13 efficiency as a function of input voltage. v out = 3.3 v. l1=10 m h, tdk slf7032 series. (1) i out = 1000 ma. (2) i out = 500 ma. (3) i out = 100 ma. (4) i out =10ma. (5) i out = 1 ma.
2003 oct 13 16 philips semiconductors preliminary speci?cation high ef?ciency auto-up/down dc/dc converter TEA1211hn 11.2 component selection 11.2.1 i nductor the inductor should have a low equivalent series resistance (esr) to reduce losses and the inductor must be able to handle the peak currents without saturating. table 3 inductor selection information 11.2.2 c apacitors for the output capacitor the esr is critical. the output voltage ripple is determined by the product of the current through the output capacitor and its esr. the lower the esr, the smaller the ripple. however, an esr less than 80 m w could result in unstable operation. table 4 input and output capacitor selection information if the i 2 c-bus interface is used to program the output voltage, use a larger input capacitor to prevent the under voltage lockout level being triggered by large current peaks drawn from this capacitor. table 5 input capacitor selection information, when i 2 c-bus is used 11.2.3 s chottky diodes the schottky diodes provide a lower voltage drop during the break-before-make time of the internal power fets. it is advised to use schottky diodes with fast recovery times. table 6 schottky selection information component value type supplier l1 6.8 m h do3316-682 coilcraft l1 10 m h slf7032t-100m1r4 tdk component value type supplier c in , c out 100 m f/10 v tps-series avx 594d-series vishay/sprague component value type supplier c in (i 2 c-bus used) 220 to 470 m f/10 v tps-series avx 594d-series vishay/sprague component type supplier d1, d2 prll5819 philips
2003 oct 13 17 philips semiconductors preliminary speci?cation high ef?ciency auto-up/down dc/dc converter TEA1211hn 11.2.4 f eedback resistors the fixed output voltage can be set with the feedback resistors r1 and r2 (see fig.11). even in case i 2 c-bus is used for programming the output voltage, these external resistors are required for start-up. the ratio of the resistors can be calculated by: , with v ref =v fb (see chapter 10). the two resistors in parallel should have a value of approximately 50 k w : 11.2.5 c urrent l imiter the maximum input peak current can be set by the current limiter as follows: w remark. the output current is not limited: in down conversion, the output current will be higher than the input current, but the maximum continuous output current is not allowed to exceed 1.7 a (rms) at 70 c. table 7 resistor selection information component value type tolerance r1, r2 v out dependent smd 1 % r lim i lim dependent smd 1 % r1 r2 ------- v out v ref ------------- 1 C = 1 r1 ------- 1 r2 ------- + 1 50 k w --------------- - ? r lim 1250 i in(peak)(max) ------------------------------ =
2003 oct 13 18 philips semiconductors preliminary speci?cation high ef?ciency auto-up/down dc/dc converter TEA1211hn 12 package outline terminal 1 index area 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 5.1 4.9 d h 3.75 3.45 y 1 5.1 4.9 3.75 3.45 e 1 3.5 e 2 3.5 0.30 0.18 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot617-3 mo-220 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot617-3 hvqfn32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 916 32 25 24 17 8 1 x d e c b a e 2 terminal 1 index area 02-04-18 02-10-22 1/2 e 1/2 e a c c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1)
2003 oct 13 19 philips semiconductors preliminary speci?cation high ef?ciency auto-up/down dc/dc converter TEA1211hn 13 soldering 13.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. 13.2 re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: below 220 c (snpb process) or below 245 c (pb-free process) C for all bga and ssop-t packages C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. below 235 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. 13.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 13.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2003 oct 13 20 philips semiconductors preliminary speci?cation high ef?ciency auto-up/down dc/dc converter TEA1211hn 13.5 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales office. 2. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 3. these transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the reflow oven. the package body peak temperature must be kept as low as possible. 4. these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 5. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 6. wave soldering is suitable for lqfp, tqfp and qfp packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 7. wave soldering is suitable for ssop, tssop, vso and vssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 8. hot bar or manual soldering is suitable for pmfp packages. package (1) soldering method wave reflow (2) bga, lbga, lfbga, sqfp, ssop-t (3) , tfbga, vfbga not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hsqfp, hsop, htqfp, htssop, hvqfn, hvson, sms not suitable (4) suitable plcc (5) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (5)(6) suitable ssop, tssop, vso, vssop not recommended (7) suitable pmfp (8) not suitable not suitable
2003 oct 13 21 philips semiconductors preliminary speci?cation high ef?ciency auto-up/down dc/dc converter TEA1211hn 14 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. 3. for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level data sheet status (1) product status (2)(3) definition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). 15 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 16 disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2003 oct 13 22 philips semiconductors preliminary speci?cation high ef?ciency auto-up/down dc/dc converter TEA1211hn 17 purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
? koninklijke philips electronics n.v. 2003 sca75 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands r54/02/pp 23 date of release: 2003 oct 13 document order number: 9397 750 12174

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